1. Field of the Invention
The present invention generally relates to semiconductor fabrication processes. More particularly, the present invention relates to the field of fabricating stacked gate structures.
2. Related Art
Semiconductor fabrication processes have made possible the fabrication of advanced integrated circuits on a semiconductor wafer. These semiconductor fabrication processes are complex, requiring extensive control and care to avoid fabricating defective integrated circuits. Moreover, within the advanced integrated circuits, specialized components are utilized to implement particular functionality. As a result, the advanced integrated circuits undergo a first group of semiconductor fabrication processes to fabricate standard components and undergo a second group of semiconductor fabrication processes to fabricate the specialized components.
In particular, a flash memory chip has a memory array and a plurality of support and control circuits. Generally, the memory array is comprised of a plurality of flash memory devices (or cells), whereas the memory array is known as the core area of the flash memory chip. Each flash memory device includes a stacked gate structure. The stacked gate includes a tunnel oxide layer, a floating gate layer for storing charge, an ONO (Oxide-Nitride-Oxide) layer, and a control gate layer for programming and erasing the flash memory device. The support and control circuits are typically comprised of standard components such as MOS (Metal Oxide Semiconductor) transistors having gate structures, whereas the support and control circuits are typically formed in the peripheral area of the flash memory chip. The gate structure includes a gate oxide layer and a gate layer.
In the fabrication of the flash memory chip, a first lithographic process, a first etching process, and a resist removal process are performed to form the stacked gate structure of the flash memory device. Separately, a second lithographic process, a second etching process, and the resist removal process are performed to form the gate structure of the MOS transistor. Typically, the stacked gate structure is formed in the core area and then the gate structure is formed in the peripheral area.
FIG. 1 illustrates a conventional stacked gate structure 90 of a flash memory device 100 after the stacked gate resist removal process has been performed. The conventional stacked gate structure 90 is formed on a substrate 60. The conventional stacked gate structure 90 includes a tunnel oxide layer 10, a floating gate layer 20 for storing charge, an ONO (Oxide-Nitride-Oxide) layer 30, and a control gate layer 40 for programming and erasing the flash memory device 100. Moreover, the conventional stacked gate structure 90 further includes an ARC (Anti-Reflective Coating) layer 50 for facilitating the lithographic process.
As noted above, a first lithographic process is performed to form a stacked gate resist layer for patterning the conventional stacked gate 90 of the flash memory device 100. The stacked gate resist layer is also deposited on the peripheral area where the support and control circuits are formed. Then, a first etching process is performed to define the conventional stacked gate 90. Thereafter, a resist removal process is performed to remove the stacked gate resist layer. Since the stacked gate resist layer has to be removed as completely as possible because the stacked gate resist layer covers the peripheral area where the support and control circuits are formed, the resist removal process is a harsh clean procedure. Thus, the conventional stacked gate structure 90 is subjected to excess clean.
As depicted in FIG. 1, the resist removal process damages the tunnel oxide layer 10 at edge 78 and at edge 76. For example, the resist removal process can damage approximately 30-50 angstroms of the tunnel oxide layer 10 at edge 78 and at edge 76. Moreover, the resist removal process damages the ONO layer 30 at edge 74 and at edge 72. For example, the resist removal process can damage approximately 30-50 angstroms of the ONO layer 30 at edge 74 and at edge 72.
The damage (manifested by degradation in dielectric properties) to the tunnel oxide layer 10 and the ONO layer 30 can cause reliability problems with charge storage/retention in the floating gate 20, reducing yield and reliability of flash memory products. Additionally, the damage can lead to fast bit problems where the flash memory device 100 is difficult to control. Unfortunately, the conventional stacked gate structure 90 again undergoes the resist removal process, magnifying the damage and problems. This time the resist removal process is associated with formation of the gate structure of a MOS transistor. Therefore, the formation of the gate structure of a MOS transistor adversely affects the stacked gate structure 90.
FIG. 2 illustrates a conventional stacked gate structure 90 of a flash memory device 100 after the gate resist removal process has been performed. As noted above, a second lithographic process is performed to form a gate resist layer for patterning the gate structure of a MOS transistor. The gate resist layer is also deposited on the conventional stacked gate structure 90. Then, a second etching process is performed to define the gate structure. However, the conventional stacked gate structure 90 does not undergo this second etching process. Thereafter, the resist removal process is performed again to remove the gate resist layer. Since the gate resist layer has to be removed as completely as possible because the gate resist layer covers the stacked gate structure 90, the resist removal process is a harsh clean procedure.
As depicted in FIG. 2, the resist removal process increases the damage to the tunnel oxide layer 10 at edge 88 and at edge 86. For example, the resist removal process can cause an additional damage to approximately another 30-50 angstroms of the tunnel oxide layer 10 at edge 88 and at edge 86. Moreover, the resist removal process increases the damage to the ONO layer 30 at edge 84 and at edge 82. For example, the resist removal process can cause an additional damage to approximately another 30-50 angstroms of the ONO layer 30 at edge 84 and at edge 82.
Thus, after two resist removal processes, the tunnel oxide layer 10 and the ONO layer 30 may be damaged by approximately 120-200 angstroms. This damage becomes more significant as the dimensions of the conventional stacked gate 90 are reduced, amplifying the yield and reliability problems described above.
What is needed is a method of protecting a stacked gate structure during fabrication. Moreover, what is needed is a method of protecting the stacked gate structure during fabrication that is simple to implement and is cost-effective.
A method of protecting a stacked gate structure during fabrication is disclosed. Additionally, the present invention provides protection for the stacked gate structure during fabrication in a manner that is simple to implement and is cost-effective.
According to one embodiment of the method of protecting the stacked gate structure of a flash memory device on a semiconductor wafer during fabrication, a resist removal process is performed to remove a first resist layer which defines the stacked gate structure. Then, a protective layer is deposited on the stacked gate structure to protect the stacked gate structure during the resist removal process. The resist removal process is repeated to remove a second resist layer which defines the gate structure of a MOS transistor. The protective layer has a sufficient thickness to protect the stacked gate structure during the resist removal process without interfering with the fabrication processes for forming the gate structure of the MOS transistor. The protective layer can be a material such as silicon-rich nitride, silicon oxynitride, or silicon dioxide. Despite undergoing two resist removal processes, the stacked gate structure suffers less damage than the convention fabrication techniques, increasing the yield and reliability of the flash memory device.